Entry Level ASIC/FPGA Design Verification Engineer
Boeing79k - 106.9k USD AnnuallyEl Segundo, USAtoday
About the job
Junior level ASIC/FPGA Design Verification role at Boeing in El Segundo, focusing on verification tasks using SystemVerilog and scripting languages
Requirements
- systemverilog
- python
- perl
- make
- git
- linux
Source: Telegram channel RVC | Global | IT Job - Remote & Relocation
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