Senior ASIC Design Engineer - Memory Subsystem
Nvidia136k - 264.5k USD AnnuallySanta Clara, United States of Americatoday
About the job
Senior-level ASIC Design Engineer position focused on memory subsystem design at Nvidia's Santa Clara office. Requires 5+ years of experience with Verilog and Perl
Requirements
- verilog
- perl
- 5 years experience
- English language proficiency
Source: Telegram channel RVC | Global | IT Job - Remote & Relocation
Employer contact is hidden
Sign up and upload your resume to unlock the direct contact for this job and a personal feed of similar ones from hundreds of Telegram channels. First 3 days free, no card.
Get the employer's contact