Sr FPGA Design Engineer (NetSec)
Palo Alto156.4k - 253k USD AnnuallyUnited States of Americatoday
About the job
Senior FPGA Design Engineer role focusing on network security (NetSec) using SystemVerilog, Verilog, and Python
Requirements
- systemverilog
- verilog
- python
Source: Telegram channel RVC | Global | IT Job - Remote & Relocation
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